This invention is in the field of integrated circuits and their manufacture. Embodiments of this invention are more particularly directed to metal-oxide-semiconductor field-effect transistors (MOSFETs) with extremely narrow gate electrodes.
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. As is fundamental in the art, reduction in the size of physical feature sizes of structures realizing transistors and other solid-state devices enables greater integration of more circuit functions per unit “chip” area, or conversely, reduced consumption of chip area for a given circuit function. The capability of integrated circuits for a given cost has greatly increased as a result of this miniaturization trend.
Advances in semiconductor technology in recent years have enabled the shrinking of the minimum device feature size (e.g., the width of the gate electrode of a metal-oxide-semiconductor (MOS) transistor, which defines the transistor channel length) into the extreme sub-micron range. State of the art transistor channel lengths are now approaching the sub-20 nanometer regime, which is on the same order of magnitude as the source and drain depletion widths. At these extremely small channel lengths, however, certain undesired effects in the electrical characteristics of MOS transistors have been observed. These undesired effects are referred to in the art as “short-channel effects”, or “SCE”.
One of these short-channel effects is referred to in the art as “ballistic transport behavior”, or surface scattering, that reduces carrier mobility to a sufficient extent to be observable in the electrical characteristics of the transistor. It has been observed that gate widths (i.e., effective channel lengths) on the order of 20 nm or less are vulnerable to this short channel effect.
Another short channel effect is referred to as drain-induced barrier lowering, which refers to the reduction of the potential barrier to carriers in the channel region in transistors with extremely short channel lengths. This barrier lowering allows electrons to travel from source to drain under Vds bias, even with the gate-to-source voltage below the threshold voltage. This subthreshold leakage is generally undesirable in digital circuits, particularly in applications that are sensitive to power consumption, such as mobile devices, implantable medical devices, and other battery-powered systems.
Another undesired subthreshold effect is referred to as the inverse narrow width effect (“INWE”), in which the threshold voltage becomes lower with narrower channel width. It has been observed that this effect is concentrated at the edges of the transistor channel, specifically at the active-to-field edge underlying the gate electrode. Leakage due to INWE typically exhibits a relatively large variance over a population of transistors, particularly in devices in which the channel edges are not well-controlled. This large variance is especially problematic in those analog circuits that rely on good matching of device characteristics.
Other short-channel effects include velocity saturation, which reduces transconductance; impact ionization, which can cause source-to-substrate leakage; and the generation and trapping of “hot” electrons, which degrades transistor performance by increasing its threshold voltage over time.
By way of further background, the scaling of MOS transistor feature sizes into the deep submicron realm has necessitated the thinning of the MOS gate dielectric layer, if conventional gate dielectric layers (e.g., silicon dioxide) are used, to an extent that can be problematic from the standpoint of gate current leakage, manufacturing yield and reliability. In response to this limitation of conventional gate dielectric material, so-called “high-k” gate dielectrics, such as hafnium oxide (HfO2), have become popular. These dielectrics have higher dielectric constants than silicon dioxide and silicon nitride, permitting those films to be physically thicker than corresponding silicon dioxide films while remaining suitable for use in high performance MOS transistors. Gate electrodes of metals and metal compounds, such as titanium nitride, tantalum-silicon-nitride, tantalum carbide, and the like are now also popular in modern MOS technology, especially in combination with these high-k gate dielectrics. These metal gate electrodes eliminate the undesired polysilicon depletion effect, which is particularly noticeable at the extremely small feature sizes required of these technologies.
By way of further background, U.S. Pat. No. 7,804,130 describes a conventional recessed-channel MOS transistor that is intended to increase the effective channel length of the transistor from that defined by the gate width. According to this approach, a “dummy” polysilicon gate electrode is formed over a dummy gate oxide structure, with spacers on the sidewall of the dummy gate electrode; source and drain implants are performed in a self-aligned manner relative to that dummy gate electrode. Following deposition of a dielectric layer overall, the dummy gate electrode and gate oxide are removed, followed by an etch of a recess into the silicon channel region between the spacers. This etch of the channel region is disclosed as preferential in the <100> silicon crystal planes, while being self-limiting in the <111> plane, which in this process results in a V-shaped recessed conduction channel along the <111> plane surfaces. Deposition of a gate dielectric over the recess, followed by deposition of the eventual gate electrode into the opening between the spacers, completes the transistor.
By way of further background, Kim, “Technology for sub-50 nm DRAM and NAND Flash Manufacturing”, Technical Digest, 2005 IEEE International Electron Device Meeting (IEEE, 2005), pp. 323-26, describes a dynamic random access memory (DRAM) array in which the cell transistors are formed as recessed channel devices.